Power semiconductor products are often fabricated using N or P channel drain-extended metal-oxide-semiconductor (DENMOS and DEPMOS, respectively) transistor devices, such as lateral diffused MOS (LDMOS) devices, for high power switching applications. DEMOS devices advantageously combine short-channel operation with high current handling capabilities, relatively low drain-source on-state resistance (Rdson), and the ability to withstand high blocking voltages without suffering voltage breakdown failure. Breakdown voltage is typically measured as drain-to-source breakdown voltage with the gate and source shorted together (BVdss).
DEMOS structures generally include thick local oxidation (LOCOS) or trench dielectric in the case of trench isolation (e.g. STI), which protects the gate dielectric edge on the drain side of the device as it would otherwise suffer dielectric breakdown, or progressive degradation during device operation. Since the field oxide thickness is usually limited by technological constraints, higher breakdown voltages typically require more lightly doped layers. However, since Rdson is proportional to the epitaxial layer resistivity, a tradeoff generally results with respect to BVdss, Rdson and BVon (breakdown with high gate-to-source voltage which is a measure of robustness). What is needed is a new process and DEMOS device architecture and/or doping that lessens this tradeoff and thus provides good device performance for BVdss, Rdson and BVon.